Integrated circuit devices typically include logic blocks that are configurable to perform any of a variety of functions. Such devices are also generally configurable to communicate with external circuitry that may be connected to them through different input-output protocols.
As an example, an integrated circuit device such as a field programmable gate array (FPGA) device may be configured as a memory controller that communicates with a memory module through a memory interface such as a double data rate (DDR) interface. As the integrated circuit device and any external circuitry connected to it may operate at different speeds, data streams read from the external circuitry may need to be properly calibrated.
In DDR communications, for example, data may be read during both the rising and falling edges of a corresponding clock signal. As such, the data stream may need to be aligned with the clock edges. Accordingly, in a memory interface, such as a DDR interface, delay lines are widely used to delay an input data stream to ensure the data transitions are properly aligned with the clock signals.
The delay lines may be configurable and may be used to provide different periods of delay to a delay circuit such as a delay locked loop (DLL). A delay line or delay circuit must therefore need to be able to provide a stable delay to ensure that the data read is properly calibrated.
A tapped delay line, typically formed by a series of CMOS inverters, is generally used to provide a fixed delay. In a tapped delay line, outputs from the series of inverters are “tapped” and coupled to a multiplexer or selector circuit. The multiplexer may then select one of the tapped outputs depending on the desired delay.
However, even though the tapped delay line may be used to provide a configurable delay period, the output delay may not be well-controlled against jitter. As the speed of the memory interface increases, the tapped delay line may experience jitter or delay variations, depending on supply voltage variations.
Furthermore, as a multiplexer may be needed to select or tap the multiple delay outputs, each delay output needs to be routed to an appropriate input terminal on the multiplexer. As such, there may be routing congestion when long wires from the outputs of the delay line are routed to the multiplexer or selector circuit. The long wire may add unwanted delay to the outputs of the delay line, causing non-uniformed outputs to be produced by the delay line.
Therefore, based on all these different factors, a fixed delay may not be obtained due to undesirable jitter and inconsistent routing delay.